DP83902AVLC datasheet(56/70 Pages) NSC

No. de pieza	DP83902AVLC

Descripción Electrónicos	ST-NICTM Serial Network Interface Controller for Twisted Pair

PDF	70 Pages

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Fabricante Electrónico	NSC [National Semiconductor (TI)]

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150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued)

DMA Control Bus Arbitration

TLF11157 – 37

Symbol

Parameter

Min

Max

Units

brqhl

Bus Clock to Bus Request High for Local DMA

brqhr

Bus Clock to Bus Request High for Remote DMA

brql

Bus Request Low from Bus Clock

backs

Acknowledge Setup to Bus Clock (Note 1)

bccte

Bus Clock to Control Enable

bcctr

Bus Clock to Control Release (Notes 2 3)

Note 1

BACK must be setup before T1 after BREQ is asserted Missed setup will slip the beginning of the DMA by four bus clocks The Bus Latency will influence

the allowable FIFO threshold

Note 2

During remote DMA transfers only a single bus transfer is performed During local DMA operations burst mode transfers are performed

Note 3

These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with

no contention

DP83902AVLC Datasheet(PDF) 56 Page - National Semiconductor (TI)

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