6

LTC2401/LTC2402

APPLICATIO S I FOR ATIO

Output Data Format

The LTC2401/LTC2402 serial output data stream is 32 bits

long. The first 4 bits represent status information indicat-

ing the sign, selected channel, input range and conversion

state. The next 24 bits are the conversion result, MSB first.

The remaining 4 bits are sub LSBs beyond the 24-bit level

that may be included in averaging or discarded without

loss of resolution.

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is LOW if the last conversion

was performed on CH0 and HIGH for CH1.

Bit 29 (third output bit) is the conversion result sign indi-

bit is LOW. The sign bit changes state during the zero

code.

Bit 28 (forth output bit) is the extended input range (EXR)

indicator. If the input is within the normal input range

0

The function of these bits is summarized in Table 1.

Table 1. LTC2401/LTC2402 Status Bits

Bit 31

Bit 30

Bit 29

Bit 28

Input Range

EOC

CH0/CH1

SIG

EXR

0

0/1

1

1

0

0/1

1

0

0

0/1

1/0

0

0

0/1

0

1

Bit 27 (fifth output bit) is the most significant bit (MSB).

Bits 27-4 are the 24-bit conversion result MSB first.

Bit 4 is the least significant bit (LSB).

Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may

be included in averaging or discarded without loss of

resolution.

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 1. Whenever CS is HIGH, SDO

remains high impedance and any SCK clock pulses are

ignored by the internal data out shift register.

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 31 (EOC) can be captured on the first rising

edge of SCK. Bit 30 is shifted out of the device on the first

MSB

EXT

SIG

CH0/CH1

1

2

3

4

5

272832

BIT 0

BIT 27

BIT 4

BIT 28

BIT 29

BIT 30

SDO

SCK

CS

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

24012 F01

Hi-Z

Figure 1. Output Data Timing