5

LTC2401/LTC2402

(Pin 4) with a 10

µF tantalum capacitor in parallel with

0.1

µF ceramic capacitor as close to the part as possible.

CH0, CH1 (Pins 4, 3): Analog Input Channels. The input

sions are performed alternately between CH0

and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on

the LTC2401.

GND (Pin 6): Ground. Shared pin for analog ground,

digital ground, reference ground and signal ground. Should

be connected directly to a ground plane through a mini-

mum length trace or it should be the single-point-ground

in a single-point grounding system.

CS (Pin 7): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion, the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW on CS wakes up the ADC. A

LOW-to-HIGH transition on this pin disables the SDO

digital output. A LOW-to-HIGH transition on CS during the

Data Output transfer aborts the data transfer and starts a

new conversion.

SDO (Pin 8): Three-State Digital Output. During the data

output period, this pin is used for serial data output. When

high impedance state. During the Conversion and Sleep

periods, this pin can be used as a conversion status out-

put. The conversion status can be observed by pulling CS

LOW.

SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal

Serial Clock Operation mode, SCK is used as digital output

for the internal serial interface clock during the data output

period. In the External Serial Clock Operation mode, SCK

is used as digital input for the external serial interface. An

internal pull-up current source is automatically activated

in Internal Serial Clock Operation mode. The Serial Clock

mode is determined by the level applied to SCK at power

up and the falling edge of CS.

controls the ADC’s notch frequencies and conversion

converter uses its internal oscillator and the digital filter’s

the converter uses this signal as its clock and the digital