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LTC2400CS8 Datasheet(PDF) 13 Page - Linear Technology

No. de pieza LTC2400CS8
Descripción Electrónicos  24-Bit uPower No Latency ADC in SO-8
PDF  40 Pages
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Fabricante Electrónico  LINER [Linear Technology]
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LTC2400CS8 Datasheet(HTML) 13 Page - Linear Technology

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LTC2400
Table 3. LTC2400 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
FO = LOW
133ms
(60Hz Rejection)
FO = HIGH
160ms
(50Hz Rejection)
External Oscillator
FO = External Oscillator
20480/fEOSCs
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = 0 and SCK
DATA OUTPUT
Internal Serial Clock
FO = LOW/HIGH
As Long As CS = LOW But Not Longer Than 1.67ms
(Internal Oscillator)
(32 SCK cycles)
FO = External Oscillator with
As Long As CS = LOW But Not Longer Than 256/fEOSCms
Frequency fEOSC kHz
(32 SCK cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 32/fSCKms
Frequency fSCK kHz
(32 SCK cycles)
APPLICATIONS INFORMATION
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2400 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2400 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2400
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
–12
–8
–4
048
12
2400 G25
–60
–70
–80
–90
–100
–110
–120
–130
–140
Figure 4. LTC2400 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state as a
function of FO.



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