LTC1420IGN datasheet(13/20 Pages) LINER

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LTC1420

DIGITAL

SYSTEM

µF

VCM

–AIN

+AIN

470pF

1420 F12

µF

VREF

GND

µF

VDD

GND

LTC1420

ANALOG GROUND PLANE

µF

VDD

µF

OVDD

GND

µF

VSS

OGND

–

ANALOG

INPUT

CIRCUITRY

Figure 13. Cross Section of LTC1420 Printed Circuit Board

AVOID BREAKING GROUND PLANE

IN THIS AREA

PLACE NON-GROUND

VIAS AWAY FROM

GROUND PLANE AND

BYPASS CAPACITORS

ANALOG

GROUND

PLANE

BYPASS

CAPACITOR

1420 F13

LTC1420

Figure 12. Power Supply Grounding

APPLICATIONS INFORMATION

are present. The SNR performance of an ADC when the

performance is limited by jitter is given by:

SNR = – 20log (2

πfINtJ)dB

where fIN is the frequency of an input sine wave and tJ is

the root-mean-square jitter due to the clock, the analog

input and the A/D aperture jitter. To minimize clock jitter,

use a clean clock source such as a crystal oscillator, treat

the clock signals as sensitive analog traces and use

dedicated packages with good supply bypassing for any

clock drivers.

Board Layout

To obtain the best performance from the LTC1420, a

printed circuit board with a ground plane is required.

Layout for the printed circuit board should ensure that

digital and analog signal lines are separated as much as

possible. In particular, care should be taken not to run any

digital track alongside an analog signal track.

An analog ground plane separate from the logic system

ground should be placed under and around the ADC.

Pins 6, 8 and 24 (GND), Pin 21 (OGND) and all other

analog grounds should be connected to this ground plane.

In single supply mode, Pin 25 (VSS) should also be

connected to this ground plane. All bypass capacitors for

the LTC1420 should also be connected to this ground

plane (Figure 12). The digital system ground should be

connected to the analog ground plane at only one point,

near the OGND pin.

The analog ground plane should be as close to the ADC as

possible. Care should be taken to avoid making holes in the

analog ground plane under and around the part. To ac-

complish this, we recommend placing vias for power and

signal traces outside the area containing the part and the

decoupling capacitors (Figure 13).

Supply Bypassing

High quality, low series resistance ceramic 1

µF capacitors

should be used at both VDD pins, VCM and VREF. If VSS is

connected to – 5V it should also be bypassed to ground

with 1

µF. In single supply operation, VSS should be

shorted to the ground plane as close to the part as

possible. If OVDD is not shorted to Pin 23 (VDD), it also

requires a 1

µF decoupling capacitor to ground. Surface

mount capacitors such as the AVX 0805ZC105KAT pro-

vide excellent bypassing in a small board space. The traces

connecting the pins and the bypass capacitors must be

kept short and should be made as wide as possible.

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