LTC1420IGN datasheet(12/20 Pages) LINER

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LTC1420

INPUT VOLTAGE (V)

–(FS – 1LSB)

FS – 1LSB

1420 F10

011…111

011…110

011…101

100…010

100…001

100…000

OVERFLOW

BIT

Figure 10. LTC1420 Transfer Characteristics

10k

µF

1420 F11

+AIN

VSS

VIN

–5V

LTC1420

–AIN

SENSE

VREF

10k

24k

100

Ω

50k

Figure 11. Offset and Full-Scale Adjust Circuit

APPLICATIONS INFORMATION

Digital Outputs and Overflow Bit (OF)

Figure 10 shows the ideal input/output characteristics for

the LTC1420. The output data is two’s complement binary

for all input ranges and for both single and dual supply

operation. One LSB = VREF/4096. To create a straight

binary output, invert the MSB (D11). The overflow bit (OF)

indicates when the analog input is outside the input range

of the converter. OF is high when the output code is 1000

0000 0000 or 0111 1111 1111.

Full-Scale and Offset Adjustment

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error should be adjusted before full-scale error. Figure 11

shows a method for error adjustment for a dual supply,

4.096V application. For zero offset error apply – 0.5mV

(i. e., – 0.5LSB) at + AIN and adjust R1 until the output code

flickers between 0000 0000 0000 and 1111 1111 1111.

For full-scale adjustment, apply an input voltage of 2.0465V

(FS – 1.5LSBs) at + AIN and adjust R2 until the output code

flickers between 0111 1111 1110 and 0111 1111 1111.

Digital Output Drivers

The LTC1420 output drivers can interface to logic operat-

ing from 3V to 5V by setting OVDD to the logic power

supply. If 5V output is desired, OVDD can be shorted to VDD

and share its decoupling capacitor. Otherwise, OVDD re-

quires its own 1

µFdecouplingcapacitor.Topreventdigital

noise from affecting performance, the load capacitance on

the digital outputs should be minimized. If large capacitive

loads are required (>30pF), external buffers or 100

Ω

resistors in series with the digital outputs are suggested.

Timing

The conversion start is controlled by the rising edge of the

CLK pin. Once a conversion is started, it cannot be stopped

or restarted until the conversion cycle is complete. Output

data is updated at the end of conversion, or about 70ns

after a conversion is begun. There is an additional two

cycle pipeline delay, so the data for a given conversion is

output two full clock cycles plus 70ns after the convert

start. Thus, output data can be latched on the third CLK

rising edge after the rising edge that samples the input.

Clock Input

The LTC1420 only uses the rising edge of the CLK pin for

internal timing, and CLK doesn’t necessarily need to have

a 50% duty cycle. For optimal AC performance, the rise

time of the CLK should be less than 5ns. If the available

clock has a rise time slower than 5ns, it can be locally sped

up with a logic gate. With single supply operation, the

clock can be driven with 5V CMOS, 3V CMOS or TTL logic

levels. With dual power supplies, the clock should be

driven with 5V CMOS levels.

As with all fast ADCs, the noise performance of the

LTC1420 is sensitive to clock jitter when high speed inputs

LTC1420IGN Datasheet(PDF) 12 Page - Linear Technology

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