AN3317

DDR memory interface

Doc ID 18249 Rev 2

11/22

5.3

Trace length matching

Always use trace length equalization to maximize the valid timing window of all signals, and

include the trace lengths inside the SPEAr device package.

A spreadsheet that compensates for the trace lengths inside the substrate is available to

compute the necessary PCB trace length offsets (contact ST).

Fly-by and balanced-T topologies each have advantages and disadvantages. Which

topology is best suited for a particular application must be evaluated on a case-by-case

basis, and take into consideration any other system constraints.

5.3.1

Address, control, and command (A/C/C) signal group,

fly-by configuration

Match trace lengths on the address, control, and command trace segments between the

SPEAr device and the first memory device in the chain.

The spreadsheet mentioned above is the easiest way to compute lengths for the A/C/C

signal group between the SPEAr device and the first memory device.

Match trace lengths for each segment group between memory devices.

Locate terminations beyond the final memory device in the chain.

Length matching is not critical between the final memory device and the termination, but

keep the termination components reasonably near the final memory device.

Ensure that the termination resistors have excellent decoupling.

5.3.2

A/C/C signal group, dual DRAM balanced-T configuration

Balanced-T topology does not require termination resistors (except for clk and nclk).

Balanced-T topology does require equal length branches on all signals within the A/C/C

signal group. Signal integrity degrades rapidly with unequal branch lengths, with serious

negative effects on signal timing.

The spreadsheet mentioned above is the easiest way to compute lengths for the A/C/C

signal group.

Place the differential clock termination resistors near the T junction.

For a single rank dual DRAM configuration, either fly-by or balanced-T topology can be

used.

5.3.3

Data signal groups

Provide matched trace lengths for each 8-bit data slice, DM signals, and DQS/DQSn

signals. It is not necessary to match the trace lengths of one data slice with the trace lengths

of any other data slice, because they are independent from a timing perspective. The

spreadsheet mentioned above is the easiest way to compute lengths for each data slice

signal group.

Figure 2 and Table 1 describe the length matching guidelines for a dual DRAM topology.

Note:

This is a guideline only; perform simulations using IBIS models on the actual PCB layout to

assess signal integrity and timing margin.