DS87C520 datasheet(15/45 Pages) DALLAS

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers

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CRYSTAL-LESS PMM

A major component of power consumption in PMM is the crystal amplifier circuit. The

DS87C520/DS83C520 allow the user to switch CPU operation to an internal ring oscillator and turn off

the crystal amplifier. The CPU would then have a clock source of approximately 2MHz to 4MHz, divided

by either 4, 64, or 1024. The ring is not accurate, so software cannot perform precision timing. However,

this mode allows an additional saving of between 0.5mA and 6.0mA, depending on the actual crystal

frequency. While this saving is of little use when running at 4 clocks per instruction cycle, it makes a

major contribution when running in PMM1 or PMM2.

PMM OPERATION

Software invokes the PMM by setting the appropriate bits in the SFR area. The basic choices are divider

speed and clock source. There are three speeds (4, 64, and 1024) and two clock sources (crystal and ring).

Both the decisions and the controls are separate. Software will typically select the clock speed first. Then,

it will perform the switch to ring operation if desired. Lastly, software can disable the crystal amplifier if

desired.

There are two ways of exiting PMM. Software can remove the condition by reversing the procedure that

invoked PMM or hardware can (optionally) remove it. To resume operation at a divide-by-4 rate under

software control, simply select 4 clocks per cycle, then crystal-based operation if relevant. When

disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated

with restarting the crystal operation. Details are described below.

There are three registers containing bits that are concerned with PMM functions. They are Power

Management Register (PMR; C4h), Status (STATUS; C5h), and External Interrupt Flag (EXIF; 91h).

Clock Divider

Software can select the instruction cycle rate by selecting bits CD1 (PMR.7) and CD0 (PMR.6) as

follows:

CD1

CD0

CYCLE RATE

Reserved

4 clocks (default)

64 clocks

1024 clocks

The selection of instruction cycle rate will take effect after a delay of one instruction cycle. Note that the

clock divider choice applies to all functions including timers. Since baud rates are altered, it will be

difficult to conduct serial communication while in PMM. There are minor restrictions on accessing the

clock selection bits. The processor must be running in a 4-clock state to select either 64 (PMM1) or 1024

(PMM2) clocks. This means software cannot go directly from PMM1 to PMM2 or visa versa. It must

return to a 4-clock rate first.

DS87C520 Datasheet(PDF) 15 Page - Dallas Semiconductor