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CS4331 Datasheet(PDF) 3 Page - Cirrus Logic

No. de pieza CS4331
Descripción Electrónicos  8 Pin Stereo D/A Converter for Digital Audio
PDF  38 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4331 Datasheet(HTML) 3 Page - Cirrus Logic

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SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 2.7V - 5.5V; Inputs: Logic 0 = 0V, Logic
1 = VA+, CL = 20 pF) Switching characteristics are guaranteed by characterization.
Parameter
Symbol
Min
Typ
Max
Units
Input Sample Rate
Fs
2
-
50
kHz
LRCK Duty Cycle (External SCLK only)
(Note 5)
30
50
70
%
MCLK Pulse Width High
MCLK / LRCK = 512
10
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 512
15
-
1000
ns
MCLK Pulse Width High
MCLK / LRCK = 384
21
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 384
21
-
1000
ns
MCLK Pulse Width High
MCLK / LRCK = 256
35
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 256
39
-
1000
ns
External SCLK Mode
SCLK Pulse Width Low
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
SCLK Period
tsclkw
1
(128)Fs
--
ns
SCLK rising to LRCK edge delay
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDATA valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDATA hold time
tsdh
20
-
-
ns
Internal SCLK Mode
SCLK Period
(Note 6)
tsclkw
1
SCLK
--
ns
SCLK rising to LRCK edge
tsclkr
-
tsclkw
2
-
µs
SDATA valid to SCLK rising setup time
tsdlrs
1
(512)Fs
+ 15
--
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 256 or 512
tsdh
1
(512)Fs
+15
--
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384
tsdh
1
(384)Fs
+15
--
ns
Notes: 5.
In Internal SCLK Mode, the Duty Cycle must be 50%
±1/2 MCLK Period.
6.
The SCLK / LRCK ratio may be either 32, 48, or 64.
CS4330, CS4331, CS4333
DS136F1
3



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