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CS4331 Datasheet(PDF) 7 Page - Cirrus Logic |
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CS4331 Datasheet(HTML) 7 Page - Cirrus Logic |
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7 / 38 page ![]() GENERAL DESCRIPTION The CS4330, CS4331, and CS4333 are complete stereo digital-to-analog systems including digital interpolation, 128 × third-order delta-sigma digi- tal-to-analog conversion, digital de-emphasis and analog filtering, Figure 2. This architecture pro- vides a high tolerance to clock jitter. The primary purpose of using delta-sigma modu- lation techniques is to avoid the limitations of laser trimmed resistive digital-to-analog con- verter architectures by using an inherently linear 1-bit digital-to-analog converter. The advantages of a 1-bit digital-to-analog converter include: ideal differential linearity, no distortion mecha- nisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resistor values. Digital Interpolation Filter The digital interpolation filter increases the sam- ple rate by a factor of 32 and is followed by a 4 × digital sample-and-hold to effectively achieve a 128 × interpolation filter. This filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate, Fs. This allows for the selection of a less complex analog filter based on out-of-band noise attenuation re- quirements rather than anti-image filtering. Following the interpolation filter, the resulting frequency spectrum has images of the input sig- nal at multiples of 128 × the input sample rate. These images are removed by the external ana- log filter. Delta-Sigma Modulator The interpolation filter is followed by a third- order delta-sigma modulator which converts the 22-bit interpolation filter output into 1-bit data at 128 × . Switched-Capacitor Filter The delta-sigma modulator is followed by a digital-to-analog converter which translates the 1-bit data into a series of charge packets. The magnitude of the charge in each packet is deter- mined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit signal. This technique greatly reduces the sensitivity to clock jitter and is a major improvement over earlier generations of 1-bit digital-to-analog converters. Interpolator Delta-Sigma Modulator DAC Analog Low-Pass Filter Analog Output Digital Input Figure 2. System Block Diagram CS4330, CS4331, CS4333 DS136F1 7 |
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