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AS3953

Datasheet - D e t a il e d D es c r i pt io n

Notes:

1. Configuration bits

b31 to b15 define AS3953 response to SAK and ATS command in ISO 14443A Protocol mode, while bits b14 to b0

actually change performance.

2. Applicable in ISO 14443A Level-3 and Level-4 Protocol modes.

3. Applicable in ISO 14443A Level-3 Protocol mode and Framing mode, in Protocol mode applicable for frames which are put in FIFO.

4. Configuration bits

fdel<1:0> are used to adjust frame delay time PCD-to-PICC. Delays caused by reader and tag resonant tanks and

AFE processing are compensated by PICC logic.Table below defines PCD-to-PICC frame delay compensation using

fdel bits.

Table 6. Configuration Word (Bits 14 to 0)

Configuration Bit

Name

Default

Function

b14

irq_pu

0

1: Send a power-up IRQ (after power-up initialization is finished)

b13

irq_l4

0

1: Send an IRQ at entry in ACTIVE(*) state (after sending SAK on Cascade

Level 2) (see note 2)

b12

mod_1

0

00: ISO 14443A Level-4 Protocol mode

01: ISO 14443A Level-3 Protocol mode

10: Framing mode

11: Transparent mode

b11

mod_0

0

b10

rxncrc

0

1: Rx – CRC is not checked, CRC part of message is also put in FIFO

(see note 3)

b9

rxbs

0

1: Rx – Bit stream mode, received bits are put in FIFO (no parity and CRC

check) (see note 3)

b8

txncrc

0

1: Tx – Do not generate CRC (see note 3)

b7

txbs

0

1: Tx – Bit stream mode, bits put in FIFO are sent without parity and CRC

generation (see note 3)

b6

fdel<1>

0

PCD-to-PICC delay adjustment (see note 4)

b5

fdel<0>

0

b4

vreg<1>

0

00: 1.8V

10: 2.7V

01: 2.0V

11: 3.3V

External Regulated voltage (VP_REG) setting

b3

vreg<0>

0

b2

rreg<1>

0

00: disabled

10: 50

Ω

01: 100

Ω

11: 25

Ω

External Regulator enable and output

resistance setting

b1

rreg<0>

0

b0

dr8

0

Reserved for internal use

fdel<1:0>

delay [ns]

delay [number of 13.56 MHz periods]

00

442.5

6

01

295.0

4

10

147.5

2

11

590.0

8