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PSD813F2 Datasheet(PDF) 104 Page - STMicroelectronics

No. de pieza PSD813F2
Descripción Electrónicos  Flash in-system programmable (ISP) peripherals
PDF  128 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD813F2 Datasheet(HTML) 104 Page - STMicroelectronics

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AC/DC parameters
PSD8XXFX
104/128
Doc ID 7833 Rev 7
tCOA
Clock to
output delay
21
30
37
+ 10
– 2
ns
tARDA
CPLD array
delay
Any macrocell
11
16
22
+ 2
ns
tMINA
Minimum
clock period
1/fCNTA
16
28
39
ns
Table 52.
CPLD macrocell asynchronous clock mode timing (5 V devices) (continued)
Symbol
Parameter
Conditions
-70
-90
-15
PT
Aloc
Turbo
off
Slew
rate
Unit
Min
Max
Min
Max
Min
Max
Table 53.
CPLD macrocell Asynchronous clock mode timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
PT
Aloc
Turbo
off
Slew
rate
Unit
Min
Max
Min
Max
Min
Max
fMAXA
Maximum
frequency
External
feedback
1/(tSA+tCOA)
21.7
19.2
16.9
MHz
Maximum
frequency
Internal
feedback
(fCNTA)
1/(tSA+tCOA–10)
27.8
23.8
20.4
MHz
Maximum
frequency
Pipelined data
1/(tCHA+tCLA)
33.3
27
24.4
MHz
tSA
Input setup time
10
12
13
+ 4
+ 20
ns
tHA
Input hold time
12
15
17
ns
tCHA
Clock high time
17
22
25
+ 20
ns
tCLA
Clock low time
13
15
16
+ 20
ns
tCOA
Clock to output
delay
36
40
46
+ 20
– 6
ns
tARD
CPLD array
delay
Any macrocell
25
29
33
+ 4
ns
tMINA
Minimum clock
period
1/fCNTA
36
42
49
ns
Obsolete
Product(s)
- Obsolete
Product(s)



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