JS28F256P33BFE datasheet(20/90 Pages) MICRON

20 / 90 page

P33-65nm

Datasheet

Aug 2009

Order Number: 320003-08

Others

Blank Check

Write

0xBC

Write

Extended Function

Interface

command(5)

Write

0xEB

Write

Sub-Op

code

Notes:

First command cycle address should be the same as the operation’s target address.

DBA = Device Base Address (NOTE: needed for dual-die 512Mbit device)

DnA = Address within the device.

IA = Identification code address offset.

CFI-A = Read CFI address offset.

WA = Word address of memory location to be written.

BA = Address within the block.

OTP-RA = OTP register address.

LRA = Lock Register address.

RCD = Read Configuration Register data on A[16:1].

ID = Identifier data.

CFI-D = CFI data on DQ[15:0].

SRD = Status Register data.

WD = Word data.

N = Word count of data to be loaded into the write buffer.

OTP-D = OTP register data.

LRD = Lock Register data.

The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This

is followed by up to 512 words of data.Then the confirm command (0xD0) is issued, triggering the array programming

operation.

The confirm command (0xD0) is followed by the buffer data.

The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1=< N <=512. The subsequent cycles load

data words into the program buffer at a specified address until word count is achieved, after the data words are loaded,

the final cycle is the confirm cycle 0xD0)

Table 7:

Command Bus Cycles (Sheet 2 of 2)

Mode

Command

Bus

Cycles

First Bus Cycle

Second Bus Cycle

Oper

Addr(1)

Data(2)

Oper

Addr(1)

Data(2)

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