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STM8S003F3U6 Datasheet(PDF) 41 Page - STMicroelectronics |
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STM8S003F3U6 Datasheet(HTML) 41 Page - STMicroelectronics |
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41 / 100 page  Option bytes 8 Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 11: Option bytes Factory default setting Option bits Option byte no. Option name Addr. 0 1 2 3 4 5 6 7 0x00 ROP [7:0] OPT0 Read-out protection (ROP) 0x4800 0x00 UBC [7:0] OPT1 User boot code(UBC) 0x4801 0xFF NUBC [7:0] NOPT1 0x4802 0x00 AFR0 AFR1 AFR2 AFR3 AFR4 AFR5 AFR6 AFR7 OPT2 Alternate function 0x4803 0xFF NAFR0 NAFR1 NAFR2 NAFR3 NAFR4 NAFR5 NAFR6 NAFR7 NOPT2 0x4804 remapping (AFR) 0x00 WWDG _HALT WWDG _HW IWDG _HW LSI_ EN HSI TRIM Reserved OPT3 Miscell. option 0x4805h 0xFF NWW G_HALT NWWDG _HW NIWDG _HW NLSI_ EN NHSI TRIM Reserved NOPT3 0x4806 0x00 PRS C0 PRS C1 CKAWU SEL EXT CLK Reserved OPT4 Clock option 0x4807 0xFF NPR SC0 NPRSC1 NCKA WUSEL NEXT CLK Reserved NOPT4 0x4808 0x00 HSECNT [7:0] OPT5 HSE clock startup 0x4809 0xFF NHSECNT [7:0] NOPT5 0x480A Table 12: Option byte description Description Option byte no. ROP[7:0] Memory readout protection (ROP) OPT0 0xAA: Enable readout protection (write access via SWIM protocol) 41/100 DocID018576 Rev 3 Option bytes STM8S003K3 STM8S003F3 |
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