ADF4001BRUZ-R7 datasheet(2/17 Pages) AD

2 / 17 page

REV.

–2–

ADF4001–SPECIFICATIONS1

(AVDD = DVDD = 3 V

10%, 5 V

10%; AVDD

≤ VP ≤ 6.0 V ; AGND = DGND =

CPGND = 0 V; RSET = 4.7 k ; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50

Parameter

B Version

Unit

Test Conditions/Comments

RF CHARACTERISTICS (3 V)

See Figure 3 for Input Circuit

RF Input Frequency

5/165

MHz min/max

RF Input Sensitivity

–10/0

dBm min/max

RF CHARACTERISTICS (5 V)

RF Input Frequency

10/200

MHz min/max

–5/0 dBm min/max

20/200

MHz min/max

–10/0 dBm min/max

REFIN CHARACTERISTICS

See Figure 2 for Input Circuit

REFIN Input Frequency

5/104

MHz min/max

For f < 5 MHz, Use DC-Coupled Square Wave

(0 to VDD)

REFIN Input Sensitivity

–5

dBm min

AC-Coupled. When DC-Coupled:

0 to VDD Max (CMOS Compatible)

REFIN Input Capacitance

pF max

REFIN Input Current

±100

µA max

PHASE DETECTOR

Phase Detector Frequency

MHz max

CHARGE PUMP

ICP Sink/Source

Programmable: See Table V

High Value

mA typ

With RSET = 4.7 k

Ω

Low Value

625

µA typ

Absolute Accuracy

2.5

% typ

With RSET = 4.7 k

Ω

RSET Range

2.7/10

Ω typ

See Table V

ICP Three-State Leakage Current

nA typ

Sink and Source Current Matching

% typ

0.5 V

≤ V

P – 0.5

ICP vs. VCP

1.5

% typ

0.5 V

≤ VCP ≤ VP – 0.5

ICP vs. Temperature

% typ

VCP = VP/2

LOGIC INPUTS

VINH, Input High Voltage

0.8

× DVDD

V min

VINL, Input Low Voltage

0.2

× DV

V max

IINH/IINL, Input Current

±1

µA max

CIN, Input Capacitance

pF max

LOGIC OUTPUTS

VOH, Output High Voltage

DVDD – 0.4

V min

IOH = 500

µA

VOL, Output Low Voltage

0.4

V max

IOL = 500

µA

POWER SUPPLIES

AVDD

2.7/5.5

V min/V max

DVDD

AVDD

AVDD/6.0

V min/V max

AVDD

≤ V

≤ 6.0 V

IDD

4 (AI

DD + DIDD)

ADF4001

5.5

mA max

4.5 mA typical

0.4

mA max

TA = 25

°C

Low Power Sleep Mode

µA typ

NOISE CHARACTERISTICS

ADF4001 Phase Noise Floor

–161

dBc/Hz typ

@ 200 kHz PFD Frequency

–153

dBc/Hz typ

@ 1 MHz PFD Frequency

Phase Noise Performance6

@ VCXO Output

200 MHz Output

–99

dBc/Hz typ

@ 1 kHz Offset and 200 kHz PFD Frequency

Spurious Signals

200 MHz Output7

–90/–95

dBc typ/dBc typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

1Operating temperature range (B Version) is –40

°C to +85°C.

2AV

DD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels.

3Guaranteed by design. Sample tested to ensure compliance.

A = 25

°C; AV

DD = DVDD = 3 V; RFIN = 100 MHz.

5The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

6The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.

REFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 kHz.

Specifications subject to change without notice.

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