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ADF4001BRUZ-R7 Datasheet(PDF) 9 Page - Analog Devices

No. de pieza ADF4001BRUZ-R7
Descripción Electrónicos  200 MHz Clock Generator PLL
PDF  17 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADF4001BRUZ-R7 Datasheet(HTML) 9 Page - Analog Devices

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REV.
ADF4001
–9–
Table IV. N Counter Latch Map
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON’T CARE BITS.
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
OPERATION
0
0CHARGE PUMP CURRENT SETTING
1 IS PERMANENTLY USED
0
1CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
1
0CHARGE PUMP CURRENT SETTING
1 IS USED
1
1CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
N13
N12
N11
N3
N2
N1
N COUNTER DIVIDE RATIO
000
..........
0011
000
..........
0102
000
..........
0113
000
..........
1004
...
..........
....
...
..........
....
...
..........
....
111
..........
100
8188
111
..........
101
8189
111
..........
110
8190
111
..........
111
8191
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0)
C1 (1)
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
CONTROL
BITS
RESERVED
13-BIT N COUNTER
DB21
RESERVED
DB22
DB23
G1
X = DON’T CARE
X
X
X
XX
X
X
X
B



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