AD6650BBCZ2 datasheet(24/44 Pages) AD

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AD6650

Rev. A | Page 24 of 44

value is −40 dBFS. When the wideband signal is below the SPB

level, the FD loop is activated. This loop overrides the slow loop

and has a programmable step size (default 0.094 dB) and a

programmable peak detect period (defaults four samples at

1.08 MHz).

UPPER THRESHOLD1

(OVER LOAD PROTECTION)

~–1dBFS

–6dBFS

–46dBFS

OPERATIONAL

RANGE

NOTES

1 ADJUSTABLE LEVEL, WITH PROGRAMMABLE STEP SIZE AND ADJUSTABLE PERIOD.

2 ADJUSTABLE LEVEL, LOOP GAIN (<1), HYSTERESIS, INTEGRATION PERIOD.

3ADJUSTABLE LEVEL, ADJUSTABLE STEP SIZE.

LOWER THRESHOLD3

(DEEP FADE PROTECTION)

REQUESTED LEVEL2

Figure 31. AGC Thresholds

SERIAL OUTPUT DATA PORT

The AD6650 has two configurable serial output ports (SDO0

and SDO1). Both ports must be identically configured and are

programmed using the same control register. The ports share a

common SFDS, SCLK, and DR pin for connection to an

external ASIC or DSP; therefore, the outputs cannot be

programmed independently.

Serial Output Data Format

The AD6650 utilizes a twos complement data format with a

selectable serial data-word length of 16 bits or 24 bits. The data

is shifted out of the device in MSB-first format.

Serial Data Frame Sync

The serial data frame sync (SDFS) pin signals the start of the

serial data frame. As channel data becomes available at the

output of the AD6650’s filters, this data is transferred into the

serial data buffer. The internal serial controller initiates the

SDFS on the next rising edge of the serial clock. In the AD6650,

there are three modes in which the frame sync can be

generated, which are described in the SDFS Modes section.

Configuring the Serial Ports

Both serial output ports must function as master serial ports. A

serial bus master provides SCLK and SDFS outputs. Serial Port 0

and Serial Port 1 must be programmed as the bus masters by

setting Bit 3 of the serial control register high.

Serial Port Data Rate

The SCLK frequency is defined by Equation 21.

SDIV

CLK

SCLK

(21)

where:

fCLK is the frequency of the master clock of the AD6650 channel.

SDIV is the serial division word for the channel.

The SDIV for Serial Port 0 and Serial Port 1 can be programmed

via Internal Control Register 0x21. Valid SDIV values are between

0 and 7, corresponding to divide ratios between 1 and 8.

Serial Output Frame Timing

The SDFS signal transitions high to signal the start of a data

frame. On the next rising edge of SCLK, the port drives the first

bit of the serial data on the SDO pin. The falling edge of SCLK

or the subsequent rising edge can then be used by the DSP to

sample the data until the required number of bits is received

(determined by the serial output port word length). If the DSP

has the ability to count bits, it can identify when the complete

frame is received.

Serial Port Timing Specifications

Figure 32 to Figure 35 indicate the timing required for the

AD6650 serial port.

SCLK

tSCLK

tSCLKH

tSCLKL

Figure 32. SCLK Timing Requirements

tSCLKH

tSCLKL

tDSCLKH

CLK

SCLK

Figure 33. SCLK Switching Characteristics (Divide-by-1)

SCLK

SDO

I15

I14

tDSDO

I13

Figure 34. Serial Output Data Switching Characteristics

SDO

IMSB

SDFS

SCLK

tDSO

IMSB1

SDFS MINIMUM

WIDTH IS ONE SCLK

FIRST DATA IS AVAILABLE THE FIRST

RISING SCLK AFTER SDFS GOES HIGH

Figure 35. Timing for Serial Output Port

SCLK

SCLK is an output on the AD6650. All outputs are switched on

the rising edge of SCLK. The SDFS pin is sampled on the falling

edge of SCLK. This allows the AD6650 to recognize the SDFS in

time to initiate a frame on the next SCLK rising edge. The

maximum speed of this port is 52 MHz.

AD6650BBCZ2 Datasheet(PDF) 24 Page - Analog Devices

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