ADP5586ACBZ-00-R7 datasheet(14/44 Pages) AD

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ADP5586

Data Sheet

Rev. 0 | Page 14 of 44

LOGIC BLOCK

Several of the ADP5586 input/output lines can be used as inputs

and outputs for implementing some common logic functions.

The R1, R2, and R3 input/output pins can be used as inputs,

and the R0 input/output pin can be used as an output for the

logic block. When the R1, R2, and R3 input lines are used, the

GPIO_4_INP_EN, GPIO_3_INP_EN, and GPIO_2_INP_EN

bits (Register 0x29, Bits[3:1]) must be enabled to accept inputs.

When the R0 pin is used as an output for the logic block, the

GPIO_1_OUT_EN bit (Register 0x27, Bit 0) must be enabled.

The outputs from the logic block can be configured to generate

interrupts. They can also be configured to generate events on

the FIFO.

Figure 19 shows a detailed diagram of the internal makeup of

the logic block, illustrating the possible logic functions that can

be implemented.

GPI EVENT

KEY EVENT

LOGIC EVENT

(R1)

LA_INV

CLR

SET

LB_INV

LC_INV

FF_SET

FF_CLR

R3_EXTEND_CFG

LOGIC_SEL[2:0]

LY_INV

(R2)

(R3)

LOGIC BLOCK

LY (R0)

LOGIC_INT

LOGIC_INT_LEVEL

LOGIC_EVENT_EN

OVRFLOW_INT

EVENT_INT

RESET_TRIG_TIME[3:0]

RESET_EVENT_A[7:0]

RESET_EVENT_B[7:0]

RESET_EVENT_C[7:0]

FIFO

EC[4:0]

LOGIC

EVENT/INT

GENERATOR

I2C BUSY

FIFO

UPDATE

Figure 18. Logic Block Overview

LA_INV

MUX

000

001

SEL[2:0]

OUT

010

011

100

101

110

111

SEL

OUT

GND

AND

XOR

IN_LA

IN_LB

IN_LC

IN_LA

SEL

OUT

AND

IN_LA

IN_LB

IN_LC

R3_EXTEND_CFG = 1

LOGIC_SEL[2:0]

LY_INV

SEL

OUT

LB_INV

SEL

OUT

IN_LB

LC_INV

SEL

OUT

IN_LC

FF_SET

FF_CLR

SEL

OUT

IN_LA

IN_LB

IN_LC

AND

SEL

OUT

XOR

IN_LA

IN_LB

IN_LC

IN_LA

IN_LB

IN_LC

XOR

CLR

SET

SEL

OUT

Figure 19. Logic Block Internal Makeup

ADP5586ACBZ-00-R7 Datasheet(PDF) 14 Page - Analog Devices

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