–3–

REV. A

AD9826

DIGITAL SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

LOGIC INPUTS

High Level Input Voltage

2.0

V

Low Level Input Voltage

0.8

V

High Level Input Current

10

µA

Low Level Input Current

10

µA

Input Capacitance

10

pF

LOGIC OUTPUTS

High Level Output Voltage

4.5

V

Low Level Output Voltage

0.1

V

High Level Output Current

50

µA

Low Level Output Current

50

µA

LOGIC OUTPUTS (with DRVDD = 3 V)

2.95

V

µA)

0.05

V

Specifications subject to change without notice.

TIMING SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

CLOCK PARAMETERS

3-Channel Pixel Rate

200

ns

1-Channel Pixel Rate

80

ns

ADCCLK Pulsewidth

30

ns

CDSCLK1 Pulsewidth

8ns

CDSCLK2 Pulsewidth

8ns

CDSCLK1 Falling to CDSCLK2 Rising

0ns

ADCCLK Falling to CDSCLK2 Rising

0ns

CDSCLK2 Rising to ADCCLK Rising

5ns

CDSCLK2 Falling to ADCCLK Falling

30

ns

CDSCLK2 Falling to CDSCLK1 Rising

5ns

Aperture Delay for CDS Clocks

2ns

SERIAL INTERFACE

Maximum SCLK Frequency

10

MHz

SLOAD to SCLK Set-Up Time

10

ns

SCLK to SLOAD Hold Time

10

ns

SDATA to SCLK Rising Set-Up Time

10

ns

SCLK Rising to SDATA Hold Time

10

ns

SCLK Falling to SDATA Valid

10

ns

DATA OUTPUTS

Output Delay

6ns

3-State to Data Valid

10

ns

Output Enable High to 3-State

10

ns

Latency (Pipeline Delay)

3 (Fixed)

Cycles

NOTES

It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.

Specifications subject to change without notice.