WM8215

Production Data

w

PD, Rev 4.3, September 2012

7

2.

Input signal limits are the limits within which the full-scale input voltage signal must lie.

Test Conditions

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Offset DAC, Monotonicity Guaranteed

Resolution

8

bits

Differential non-linearity

DNL

0.15

LSB

Integral non-linearity

INL

0.4

LSB

Step size

2.00

mV/step

Output voltage

Code 00(hex)

Code FF(hex)

-255

+255

mV

mV

Programmable Gain Amplifier

Resolution

9

bits

Gain

]

:

[

PGA

*

.

.

0

8

511

34

7

66

0



V/V

Max gain, each channel

8

V/V

Min gain, each channel

0.66

V/V

Gain error, each channel

3

%

Analogue to Digital Converter

Resolution

10

bits

Speed

60

MSPS

Full-scale input range

(2*(VRT-VRB))

LOWREFS=0

1.9

2

2.2

V

LOWREFS=1

1.2

V

DIGITAL SPECIFICATIONS

Digital Inputs

High level input voltage

0.7

 DVDD2

V

Low level input voltage

0.2

 DVDD2

V

High level input current

1

A

Low level input current

1

A

Input capacitance

5

pF

Digital Outputs

High level output voltage

DVDD2 - 0.5

V

Low level output voltage

0.5

V

High impedance output current

1

A

Digital IO Pins

Applied high level input voltage

0.7

 DVDD2

V

Applied low level input voltage

0.2

 DVDD2

V

High level output voltage

DVDD2 - 0.5

V

Low level output voltage

0.5

V

Low level input current

1

A

High level input current

1

A

Input capacitance

5

pF

High impedance output current

1

A

Supply Currents



Total supply current

 active

116

mA



Analogue supply current – active

(three channel mode)

105

mA

Digital supply current – active

(three channel mode)

11

mA

Supply current

 full power down

mode

20

A