WM8215 datasheet(4/31 Pages) WOLFSON

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WM8215

Production Data

PD, Rev 4.3, September 2012

PIN DESCRIPTION

NAME

TYPE

DESCRIPTION

RSMP

Digital input

Reset sample pulse (when CDS=1) or clamp control

MCLK

Digital input

Master (ADC) clock. This clock determines the ADC conversion rate.

DGND

Supply

Digital ground.

SEN

Digital input

Enables the serial interface when high.

DVDD2

Supply

Digital supply, all digital I/O pins.

SDI

Digital input

Serial data input.

SCK

Digital input

Serial clock.

No connect

No internal connection.

No connect

No internal connection.

Digital output data bus. ADC output data (d9:d0) is available in 10-bit parallel

format.

OP[0]

Digital output

d0 (LSB)

OP[1]

Digital output

OP[2]

Digital output

OP[3]

Digital output

OP[4]

Digital output

OP[5]

Digital output

OP[6]

Digital output

OP[7]

Digital output

OP[8]

Digital output

OP[9]/SDO

Digital output

d9 (MSB)

Alternatively, pin OP[9]/SDO may be used to output register read-back data when

OEB=0, OPD(register bit)=0 and SEN has been pulsed high. See Serial Interface

description in Device Description section for further details.

AVDD

Supply

Analogue supply. This must be operated at the same potential as DVDD1.

AGND1

Supply

Analogue ground.

VRB

Analogue output

Lower reference voltage.

This pin must be connected to AGND via a decoupling capacitor.

VRT

Analogue output

Upper reference voltage.

This pin must be connected to AGND via a decoupling capacitor.

VRX

Analogue output

Input return bias voltage.

This pin must be connected to AGND via a decoupling capacitor.

VRLC/VBIAS

Analogue I/O

Selectable analogue output voltage for RLC or single-ended bias reference.

This pin would typically be connected to AGND via a decoupling capacitor.

VRLC can be externally driven if programmed Hi-Z.

BINP

Analogue input

Blue channel input video.

GINP

Analogue input

Green channel input video.

RINP

Analogue input

Red channel input video.

AGND2

Supply

Analogue ground.

DVDD1

Supply

Digital supply for logic and clock generator. This must be operated at the same

potential as AVDD.

OEB

Digital input

Output Hi-Z control. All digital outputs set to high-impedance state when input pin

OEB=1 or register bit OPD=1.

VSMP

Digital input

Video sample pulse.

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