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STRH8N10 Datasheet(PDF) 5 Page - STMicroelectronics

No. de pieza STRH8N10
Descripción Electrónicos  Rad-Hard N-channel 100 V, 6 A Power MOSFET
PDF  18 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STRH8N10 Datasheet(HTML) 5 Page - STMicroelectronics

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STRH8N10
Electrical characteristics
Doc ID 010029 Rev 2
5/18
2
Electrical characteristics
(TCASE = 25°C unless otherwise specified).
2.1
Pre-irradiation
Table 5.
On/off states
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IDSS
Zero gate voltage drain
current (VGS = 0)
100% BVDss
1mA
80% BVDss
80% BVDss, TC = 125 °C
10
100
µA
IGSS
Gate body leakage current
(VDS = 0)
VGS = 20 V
VGS = -20 V
VGS = 20 V, TC = 125 °C
VGS = -20 V, TC = 125 °C
-100
-200
100
200
nA
VGS(th)
Gate threshold voltage
VDS =VGS, ID = 1mA
VDS =VGS, ID = 1mA ,
TC = 125 °C
VDS =VGS, ID = 1mA ,
TC = -55 °C
2
1.5
2.1
4.5
3.7
5.5
V
RDS(on)
Static drain-source on
resistance
VGS = 12 V, ID = 4 A
VGS = 12 V, ID = 4 A,
TC = 125 °C
0.30
0.72
Table 6.
Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Coss
(1)
Crss
1.
This value is guaranteed over the full range of temperature.
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f=1 MHz,
VGS=0V
527
76
31
659
95
39
791
114
47
pF
pF
pF
Coss eq.
(1) Equivalent output
capacitance (2)
2.
This value is defined as the ratio between the Qoss and the voltage value applied.
VDD = 80 V, VGS=0V
162
pF
Qg
Qgs
Qgd
Total gate charge
Gate-to-source charge
Gate-to-drain (“Miller”)
charge
VDD = 50 V, ID = 4 A,
VGS= 12 V
15
3
4
18.5
4
5.5
22
5
7
nC
nC
nC
RG
(3)
3.
Not tested, guaranteed by process.
Gate input resistance
f=1MHz gate DC bias=0
test signal level=20mV
open drain
1.6



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