TNETEL1200

EtherLoop

™ MODEM

SPHS003D – FEBRUARY 1999 – REVISED JUNE 1999

15

POST OFFICE BOX 655303

microprocessor interface (see Figure 7)

NO.

MIN

MAX

UNIT

1

tsu

Setup time, UPADDR before UPCSN low – address is latched by UPCSN falling edge

2

ns

2

td

Delay time, read data valid after last of UPCSN and UPOEN low

20

ns

3

tsu

Setup time, address before UPCSN low

2

ns

4

tsu

Setup time, write data valid before UPWRN high

15

ns

5

th

Hold time, write data valid after UPWRN high

5

ns

6

td

Delay time, data high Z after UPOEN high

20

ns

UPCSN

UPADDR7–

UPADDR0

UPRWN

UPOEN

Read

Write

1

3

6

2

4

5

Data

Figure 7. Microprocessor Interface

XTAL (see Figure 8)

NO.

MIN

MAX

UNIT

1

tc(XTAL)

Cycle time, XTAL

12.5

ns

2

tw(XTALH) Pulse duration, XTAL high

5

ns

3

tw(XTALL)

Pulse duration, XTAL low

5

ns

XTAL

2

3

1

Figure 8. XTAL