TNETEL1200

EtherLoop

™ MODEM

SPHS003D – FEBRUARY 1999 – REVISED JUNE 1999

13

POST OFFICE BOX 655303

–0.5 V to 4.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6-V fail-safe TTL/LVCMOS

–0.5 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-V tolerant TTL/LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6-V fail-safe TTL/LVCMOS

–0.5 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-V tolerant TTL/LVCMOS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . .

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (100 pF, 1.5 k

Ω)

4.0 kV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Latchup immunity

>250 mA at 25

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. Applies to external input and bidirectional buffers (for 5-V tolerant, used VI >)

2. Applies to external output and bidirectional buffers (for 5-V tolerant, used VO >)

recommended operating conditions

MIN

MAX

UNIT

VCC

Supply voltage

3

3.6

V

VI

Input voltage

TTL/LVCMOS

0

VCC

V

VI

Input voltage

5-V tolerant TTL/LVCMOS

V

VO

Output voltage

TTL/LVCMOS

0

VCC

V

VO

Output voltage

5-V tolerant TTL/LVCMOS

V

VIH

High level input voltage

TTL/LVCMOS

2

VCC

V

VIH

High-level input voltage

5-V tolerant TTL/LVCMOS

V

VIL

Low level input voltage

TTL/LVCMOS

0

0.8

V

VIL

Low-level input voltage

5-V tolerant TTL/LVCMOS

0.8

V

tr

Input transition (tr and tf) time (10% to 90%)

6

ns

TA‡

Ambient temperature

–40

85

°C

TJ

Junction temperature (commercial specification)

–40

125

°C

‡ TA is measured at the surface of the package. No airflow or heatsink is assumed. The maximum ambient temperature is calculated considering

PMAX, R

θJA, and TJ.

electrical characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = rated

VCC–0.6

V

VOL

High-level output voltage

IOL = rated

0.5

V

Vhys

Hysteresis (VT+ – VT–)

0.4

V

IIL

Low level input current (Vi =VIL min)

3.6-V failsafe

±1

µA

IIL

Low-level input current (Vin = VIL min)

5-V tolerant

±20

µA

IIH

High level input current (Vi =VIH max)

3.6-V failsafe

±1

µA

IIH

High-level input current (Vin = VIH max)

5-V tolerant

±20

µA

IIZ§

3-state output high-impedance current

±20

µA

§ 3-state or open-drain output must be in high-impedance state.