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SL4017B Datasheet(PDF) 1 Page - System Logic Semiconductor

No. de pieza SL4017B
Descripción Electrónicos  Counter/Divider
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Fabricante Electrónico  SLS [System Logic Semiconductor]
Página de inicio  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL4017B Datasheet(HTML) 1 Page - System Logic Semiconductor

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SL4017B
System Logic
Semiconductor
SL
S
Counter/Divider
High-Voltage Silicon-Gate CMOS
The SL4017B is 5-stage Johnson counter having 10
decoded outputs. Inputs include a CLOCK, a RESET, and a
CLOCK INHIBIT signal. Schmitt trigger action in the
CLOCK input circuit provides pulse shaping that allows
unlimited clock input pulse rise and fall times.
The counter is advanced one count at the positive
clock signal transition if the CLOCK INHIBIT signal is
low. Counter advancement via the clock line is inhibited
when the CLOCK INHIBIT signal is high. A high RESET
signal clears the counter to its zero count. Use of the
Johnson counter configuration permits high-speed
operation, 2-input decode-gating and spike-free decoded
outputs. Anti-lock gating is provided, thus assuring proper
counting sequence. The decoded outputs are normally low
and go high only at their respective decoded time slot.
Each decoded output remains high for one full clock cycle.
A CARRY-OUT signal completes one cycle every 10 clock
input cycles in the SL4017B.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full
package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package
temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4017BN Plastic
SL4017BD SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND


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