LTC1609 datasheet(4/22 Pages) LINER

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LTC1403-1/LTC1403A-1

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TIMING CHARACTERISTICS

DIGITAL INPUTS AND DIGITAL OUTPUTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VIH

High Level Input Voltage

VDD = 3.3V

2.4

VIL

Low Level Input Voltage

VDD = 2.7V

0.6

IIN

Digital Input Current

VIN = 0V to VDD

±10

µA

CIN

Digital Input Capacitance

(Note 20)

VOH

High Level Output Voltage

VDD = 3V, IOUT = –200µA

2.5

2.9

VOL

Low Level Output Voltage

VDD = 2.7V, IOUT = 160µA

VDD = 2.7V, IOUT = 1.6mA

0.05

0.10

0.4

IOZ

Hi-Z Output Leakage DOUT

VOUT = 0V to VDD

±10

µA

COZ

Hi-Z Output Capacitance DOUT

ISOURCE

Output Short-Circuit Source Current

VOUT = 0V, VDD = 3V

ISINK

Output Short-Circuit Sink Current

VOUT = VDD = 3V

POWER REQUIREMENTS The

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 17)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VDD

Supply Voltage

2.7

3.6

IDD

Positive Supply Voltage

Active Mode

Nap Mode

Sleep Mode (LTC1403-1)

Sleep Mode (LTC1403A-1)

4.7

1.1

1.5

µA

Power Dissipation

Active Mode with SCK in Fixed State (Hi or Lo)

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. VDD = 3V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSAMPLE(MAX) Maximum Sampling Frequency per Channel

(Conversion Rate)

2.8

MHz

tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period)

357

tSCK

Clock Period

(Note 16)

19.8

10000

tCONV

Conversion Time

(Note 6)

SCLK cycles

Minimum Positive or Negative SCLK Pulse Width

(Note 6)

CONV to SCK Setup Time

(Notes 6, 10)

Nearest SCK Edge Before CONV

(Note 6)

Minimum Positive or Negative CONV Pulse Width

(Note 6)

SCK to Sample Mode

(Note 6)

CONV to Hold Mode

(Notes 6, 11)

1.2

16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)

(Notes 6, 7, 13)

Minimum Delay from SCKto Valid Data

(Notes 6, 12)

SCK to Hi-Z at SDO

(Notes 6, 12)

t10

Previous SDO Bit Remains Valid After SCK

(Notes 6, 12)

t12

VREF Settling Time After Sleep-to-Wake Transition

(Notes 6, 14)

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V

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