TMS570LS3137 datasheet(78/159 Pages) TI

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TMS570LS3137

SPNS162.

– SEPTEMBER 2011

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4.10.2 Main Features of Flash Module

•

Support for multiple flash banks for program and/or data storage

•

Simultaneous read access on a bank while performing program or erase operation on any other bank

•

Integrated state machines to automate flash erase and program operations

•

Software interface for flash program and erase operations

•

Pipelined mode operation to improve instruction access interface bandwidth

•

Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU

– Error address is captured for host system debugging

•

Support for a rich set of diagnostic features

4.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection

(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of

instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on

the 64 bits received and compares it with the ECC code returned by the flash module. A signle-bit error is

corrected and flagged by the CPU, while a multi-bit error is only flagged. The CPU signals an ECC error

via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the

"X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0

;Enabling Event monitor states

ORR r1, r1, #0x00000010

MCR p15,#0,r1,c9,c12,#0

;Set 4th bit (‘X’) of PMNC register

MRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM

and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC

checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN

bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1

ORR r1, r1, #0x0e000000

;Enable ECC checking for ATCM and BTCMs

DMB

MCR p15, #0, r1, c1, c0, #1

4.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 3.4.

System Information and Electrical Specifications

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