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R5F52108ADFF Datasheet(PDF) 29 Page - Renesas Technology Corp |
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R5F52108ADFF Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 92 page  R01DS0041EJ0050 Rev.0.50 Page 29 of 90 Apr 15, 2011 RX210 Group 2. CPU Under development Preliminary document Specifications in this document are tentative and subject to change. 2.2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.2.2 Control Registers This CPU has the following eight control registers. Interrupt stack pointer (ISP) User stack pointer (USP) Interrupt table register (INTB) Program counter (PC) Processor status word (PSW) Backup PC (BPC) Backup PSW (BPSW) Fast interrupt vector register (FINTV) |
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