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ISL89166 Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL89166 Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 13 page ![]() ISL89166, ISL89167, ISL89168 9 FN7720.0 January 14, 2011 Power Dissipation of the Driver The power dissipation of the ISL89166, ISL89167, ISL89168 is dominated by the losses associated with the gate charge of the driven bridge FETs and the switching frequency. The internal bias current also contributes to the total dissipation but is usually not significant as compared to the gate charge losses. Figure 19 illustrates how the gate charge varies with the gate voltage in a typical power MOSFET. In this example, the total gate charge for Vgs = 10V is 21.5nC when VDS = 40V. This is the charge that a driver must source to turn-on the MOSFET and must sink to turn-off the MOSFET. Equation 1 shows calculating the power dissipation of the driver: Where: freq = Switching frequency, VGS = VDD bias of the ISL89166, ISL89167, ISL89168 Qc = Gate charge for VGS IDD(freq) = Bias current at the switching frequency (see Figure 9) rDS(ON) = ON-resistance of the driver Rgate = External gate resistance (if any). Note that the gate power dissipation is proportionally shared with the external gate resistor. When sizing an external gate resistor, do not overlook the power dissipated by this resistor. Typical Application Circuit FIGURE 17. SETTING DELAYS A RESISTOR INx OUTx RDTx ISL89166 FIGURE 18. SETTING DELAYS WITH A RCD NETWORK INx Rdel cdel D OUTx ISL89160 Qg, GATE CHARGE (nC) 12 10 8 6 4 2 0 02468 10 12 14 16 18 20 22 24 FIGURE 19. MOSFET GATE CHARGE vs GATE VOLTAGE VDS = 64V VDS = 40V (EQ. 1) PD 2Qc freq VGS Rgate Rgate rDS ON () + ------------------------------------------ IDD freq () V DD • + • • • • = PWM LR LL LL Red dashed lines emphasize the resonant switching delay of the low- side bridge FETs ZVS Full Bridge T1A T1B T2 U1B U2A U2B QUL QUR QLL QLR LL LR SQR SQR R VGLL VGUL VGLR VGUR VGLR VGUL VGUR VGLL Vbridge ISL89162 U1A ½ ISL89166 ½ ISL89166 LL: lower left LR: lower right UL: upper left UR: upper right GLL: gate lower left |
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