PIC16F720-ESLASHML datasheet(163/244 Pages) MICROCHIP

163 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 163

PIC16F/LF720/721

18.5

Writing to Flash Program Memory

A word of the Flash program memory may only be

written to if the word is in an unprotected segment of

memory.

Flash program memory may only be written to if the

destination address is in a segment of memory that is

not write-protected, as defined in bits WRT<1:0> of the

Configuration Word Register 2. Flash program memory

must be written in 32-word rows. See Figure 18-2 for

more details. A row consists of 32 words with sequen-

tial addresses, with a lower boundary defined by an

address, where PMADR<4:0>= 00000. All row writes to

program memory are done as 32-word erase and one

to 32-word write operations. The write operation is

edge-aligned. Crossing boundaries is not recom-

mended, as the operation will only affect the new

boundary, wrapping the data values at the same time.

Once the write control bit is set, the Program Memory

(PM) controller will immediately write the data. Program

execution is stalled while the write is in progress.

To erase a program memory row, the address of the

row

erase

must

loaded

into

the

PMADRH:PMADRL register pair. A row consists of 32

words so, when selecting a row, PMADR<4:0> are

ignored. After the Address has been set up, then the

following sequence of events must be executed:

Set the WREN and FREE control bits of the

PMCON1 register.

Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

Set the WR control bit of the PMCON1 register.

To write program data, it must first be loaded into the

buffer latches (see Figure 18-2). This is accomplished

by first writing the destination address to PMADRL and

PMADRH and then writing the data to PMDATA and

PMDATH. After the address and data have been set

up, then the following sequence of events must be exe-

cuted:

Set the WREN control bit of the PMCON1

Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

Set the WR control bit of the PMCON1 register.

All 32 buffer register locations should be written to with

correct data. If less than 32 words are being written to

in the block of 32 words, then a read from the program

memory location(s) not being written to must be

performed. This takes the data from the program

location(s) not being written and loads it into the

PMDATL and PMDATH registers. Then, the sequence

of events to transfer data to the buffer registers must be

executed.

When the LWLO bit is ‘1’, the write sequence will only

load the buffer register and will not actually initiate the

write to program Flash:

Set the WREN and LWLO bits of the PMCON1

Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

Set control bit WR of the PMCON1 register to

begin the write operation.

To transfer data from the buffer registers to the program

memory, the last word to be written should be written to

the

PMDATH:PMDATL

pair.

Then,

the

following sequence of events must be executed:

Clear the LWLO bit of the PMCON1 Register.

Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

Set control bit WR of the PMCON1 register to

begin the write operation.

Two NOP must follow the setting of the WR bit.

This is necessary to provide time for the address and to

be provided to the program Flash memory to be put in

the write latches.

No automatic erase occurs upon the initiation of the

write; if the program Flash needs to be erased before

writing, the row (32 words) must be previously erased.

After the “BSF PMCON1, WR” instruction, the processor

requires two cycles to set up the erase/write operation.

The user must place two NOP instructions after the WR

bit is set. These two instructions will also be forced in

hardware to NOP, but if an ICD break occurs at this

point, the forcing to NOP will be lost.

Note:

Self-write execution to Flash memory can-

not be done while running in low power

PFM and Voltage Regulator modes.

Therefore, executing a self-write will put

the PFM and voltage regulator into High

Power mode for the duration of the

sequence.

Note:

An ICD break that occurs during the 55h -

AAh - Set WR bit sequence will interrupt

the timing of the sequence and prevent

the unlock sequence from occurring. In

this case, no write will be initiated, as

there was no operation to complete.

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