PIC16F720-ESLASHML datasheet(137/244 Pages) MICROCHIP

137 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 137

PIC16F/LF720/721

16.3.2.3

AUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 16.3.1.4 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE interrupt enable bit

of the PIE1 register is set, the interrupt generated will

wake the device from Sleep and execute the next

instruction. If the GIE bit is also set, the program will

branch to the interrupt vector.

16.3.2.4

Synchronous Slave Reception Setup

Set the SYNC and SPEN bits and clear the

CSRC bit.

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set the RX9 bit.

Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

Set the CREN bit to enable reception.

The RCIF bit of the PIR1 register will be set

when reception is complete. An interrupt will be

generated if the RCIE bit of the PIE1 register

was set.

If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

TABLE 16-9:

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE

PEIE

TMR0IE

INTE

RABIE

TMR0IF

INTF

RABIF

0000 000x

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

RCREG

AUSART Receive Data Register

0000 0000

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

1111 1111

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

Legend:

= unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.

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