PIC16F720-ESLASHML datasheet(141/244 Pages) MICROCHIP

141 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 141

PIC16F/LF720/721

17.1.1

MASTER MODE

In Master mode, data transfer can be initiated at any

time because the master controls the SCK line. Master

mode

determines

when

the

slave

(Figure 17-1,

Processor 2) transmits data via control of the SCK line.

17.1.1.1

Master Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

first. The SSPBUF register holds the data that is written

out of the master until the received data is ready. Once

the eight bits of data have been received, the byte is

moved to the SSPBUF register. The Buffer Full Status

bit, BF of the SSPSTAT register, and the SSP Interrupt

Flag bit, SSPIF of the PIR1 register, are then set.

Any write to the SSPBUF register during transmission/

reception of data will be ignored and the Write Collision

Detect bit, WCOL of the SSPCON register, will be set.

User software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data is written to the SSPBUF. The BF bit of the

SSPSTAT register is set when SSPBUF has been

loaded with the received data (transmission is

complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. The SSP interrupt may be used to

determine

when

the

transmission/reception

complete and the SSPBUF must be read and/or

written. If interrupts are not used, then software polling

can be done to ensure that a write collision does not

occur. Example 17-1 shows the loading of the SSPBUF

(SSPSR) for data transmission.

17.1.1.2

Enabling Master I/O

To enable the serial port, the SSPEN bit of the

SSPCON register, must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON register and then set the SSPEN bit. If a

Master mode of operation is selected in the SSPM bits

of the SSPCON register, the SDI, SDO and SCK pins

will be assigned as serial port pins.

For these pins to function as serial port pins, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

• SDI configured as input

• SDO configured as output

• SCK configured as output

17.1.1.3

Master Mode Setup

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is loaded with a byte

value. If the master is only going to receive, SDO output

could be disabled (programmed and used as an input).

The SSPSR register will continue to shift in the signal

present on the SDI pin at the programmed clock rate.

When initializing SPI Master mode operation, several

options need to be specified. This is accomplished by

programming the appropriate control bits in the

SSPCON and SSPSTAT registers. These control bits

allow the following to be specified:

• SCK as clock output

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

• Clock bit rate

In Master mode, the SPI clock rate (bit rate) is user

selectable to be one of the following:

•FOSC/4 (or TCY)

•FOSC/16 (or 4

 TCY)

•FOSC/64 (or 16

 TCY)

• (Timer2 output)/2

This

allows

maximum

data

rate

5 Mbps

(at FOSC =16MHz).

Figure 17-3 shows the waveforms for Master mode.

The clock polarity is selected by appropriately program-

ming the CKP bit of the SSPCON register. When the

CKE bit is set, the SDO data is valid before there is a

clock edge on SCK. The sample time of the input data

is shown based on the state of the SMP bit and can

occur at the middle or end of the data output time. The

time when the SSPBUF is loaded with the received

data is shown.

17.1.1.4

Sleep in Master Mode

In Master mode, all module clocks are halted and the

transmission/reception will remain in their current state,

paused, until the device wakes from Sleep. After the

device wakes up from Sleep, the module will continue

to transmit/receive data.

Note:

The SSPSR is not directly readable or

writable and can only be accessed by

addressing the SSPBUF register.

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