PIC16F720-ESLASHML datasheet(134/244 Pages) MICROCHIP

134 / 244 page

PIC16F/LF720/721

DS41430A-page 134

 2010 Microchip Technology Inc.

16.3.1.4

Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

AUSART is configured for synchronous master receive

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

received into the RSR, the RCIF bit of the PIR1 register

is set and the character is automatically transferred to

the two character receive FIFO. The Least Significant

eight bits of the top character in the receive FIFO are

available in RCREG. The RCIF bit remains set as long

as there are un-read characters in the receive FIFO.

16.3.1.5

Slave Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The TX/

CK pin output driver is automatically disabled when the

device is configured for synchronous slave transmit or

receive operation. Serial data bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One data bit is transferred for each clock cycle.

Only as many clock cycles should be received as there

are data bits.

16.3.1.6

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register.

16.3.1.7

Receiving 9-bit Characters

The AUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the AUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

Address detection in Synchronous modes is not

supported, therefore the ADDEN bit of the RCSTA

16.3.1.8

Synchronous Master Reception

Setup

Initialize the SPBRG register for the appropriate

baud rate. Set or clear the BRGH bit, as

required, to achieve the desired baud rate.

Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

Ensure bits CREN and SREN are clear.

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set bit RX9.

Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

Interrupt flag bit RCIF of the PIR1 register will be

set when reception of a character is complete.

An interrupt will be generated if the RCIE inter-

rupt enable bit of the PIE1 register was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

resets the AUSART.

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