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PIC16F727-E/ML Datasheet(PDF) 49 Page - Microchip Technology

No. de pieza PIC16F727-E/ML
Descripción Electrónicos  28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
PDF  302 Pages
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Fabricante Electrónico  MICROCHIP [Microchip Technology]
Página de inicio  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F727-E/ML Datasheet(HTML) 49 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS41341E-page 49
PIC16F72X/PIC16LF72X
4.5.4
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 4-4.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User
software
should
ensure
the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-4:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit
1
= Timer1 Gate is inactive
0
= Timer1 Gate is active
bit 6
ADIF: A/D Converter Interrupt Flag bit
1
= A/D conversion complete (must be cleared in software)
0
= A/D conversion has not completed or has not been started
bit 5
RCIF: USART Receive Interrupt Flag bit
1
= The USART receive buffer is full (cleared by reading RCREG)
0
= The USART receive buffer is not full
bit 4
TXIF: USART Transmit Interrupt Flag bit
1
= The USART transmit buffer is empty (cleared by writing to TXREG)
0
= The USART transmit buffer is full
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1
= The Transmission/Reception is complete (must be cleared in software)
0
= Waiting to Transmit/Receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare mode:
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1
= A Timer2 to PR2 match occurred (must be cleared in software)
0
= No Timer2 to PR2 match occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1
= The TMR1 register overflowed (must be cleared in software)
0
= The TMR1 register did not overflow



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