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IP4365CX11/P Datasheet(PDF) 2 Page - NXP Semiconductors |
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IP4365CX11/P Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 12 page ![]() IP4365CX11_1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 26 March 2010 2 of 12 NXP Semiconductors IP4365CX11 Integrated SIM card passive filter array and USB ESD protection 2. Pinning information 2.1 Pinning 2.2 Pin description 3. Ordering information Fig 1. Pin configuration 008aaa218 transparent top view, solder balls facing down bump A1 index area 321 A B C D Table 1. Pinning Pin Description A1 internal pin RST or I/O channel A2 ground A3 external pin RST or I/O channel B1 internal pin CLK channel B2 not connected (missing ball) B3 external pin CLK channel C1 internal pin I/O or RST channel C2 ground C3 external pin I/O or RST channel D1 external ESD protection (USB data or supply) D2 external ESD protection (USB data or supply) D3 external ESD protection (USB data or supply) Table 2. Ordering information Type number Package Name Description Version IP4365CX11/P WLCSP11 wafer level chip-size package; 11 bumps (3 × 4 - B2) IP4365CX11/P |
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