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TLE8201R Datasheet(PDF) 23 Page - Infineon Technologies AG |
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TLE8201R Datasheet(HTML) 23 Page - Infineon Technologies AG |
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23 / 45 page ![]() TLE 8201R Data Sheet Rev. 2.0 23 2006-06-07 power Stage x, xsel1 and xsel2 are LOW, the power stage x is controlled only via the SPI control bit xON. If the selection bit xsel1 is HIGH and the control bit xON is also high, the power stage x is controlled by the PWM1 pin (xsel2 and PWM2, respectively). The behavior is shown in the pricipal schematic and truth table below. In terms of power dissipation due to switching loss, a PWM frequency below 200 Hz is recommended. Figure 8 PWM input and SPI control registers OUT x PWM1 & & S P I CLK DO DI CSN Gate driver xON xsel1 1 x ∈ {LS1, LS2, LS3, HS7, HS8, HS9, HS10, HS11} PWM2 1 xsel2 & >=1 control logic of power transistor x power transistor x |
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