TLE8201R datasheet(14/45 Pages) INFINEON

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TLE 8201R

Data Sheet Rev. 2.0

2006-06-07

4.3

SPI

4.3.1

General

The SPI is used for bidirectional communication with a control unit. The TLE 8201R acts

as SPI-slave and the control unit acts as SPI-master. The 16-bit control word is read via

the DI serial data input. The status word appears synchronously at the DO serial data

output. The communication is synchronized by the serial clock input CLK.

Standard data transfer timing is shown in Figure 3. The clock polarity is data valid on

falling edge. CLK must be low during CSN transition. The transfer is MSB first.

The transmission cycle begins when the chip is selected with the chip-select-not (CSN)

input (H to L). Then the data is clocked through the shift register. The transmission ends

when the CSN input changes from L to H and the word which has been read into the shift

thereby releasing the DO bus circuit for other uses. The SPI allows to parallel multiple

SPI devices by using multiple CSN lines. The SPI can also be used with other SPI-

devices in a daisy-chain configuration.

Figure 3

SPI standard data transfer timing

4.3.2

The 16-bit SPI frame is composed of an addressable block, an address-independent

block and a 2-bit address as shown in Figure 4.

The control word transmitted from the master to the TLE 7201R is executed at the end

of the SPI transmission (CSN L -> H) and remains valid until a different control word is

transmitted or a power on reset occurs. At the beginning of the SPI transmission (CSN

15 14 13 12 11 10

CLK

CSN

CSN High to Low & rising edge of SCLK: SDO is enabled. Status information is transfered to Output Shift Register

CSN Low to High: Data from Shift-Register is transfered to Output Driver Logic

previous Status

actual Data

SDI: Data will be accepted on the falling edge of CLK-Signal

SDO: State will change on the rising edge of CLK-Signal

time

15 14

new Data

actual Status

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