AD6642BBCZRL datasheet(21/32 Pages) AD

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AD6642

Rev. 0 | Page 21 of 32

DIGITAL OUTPUTS

The AD6642 output drivers are configured to interface with

LVDS outputs using a DRVDD supply voltage of 1.8 V. The

output bits are DDR LVDS as shown in Figure 2. Applications

that require the ADC to drive large capacitive loads or large

fanouts may require external buffers or latches.

As described in Application Note AN-877, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary or twos complement when using the SPI control.

TIMING

The AD6642 provides latched data with a pipeline delay of

nine clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD6642. These transients can degrade converter dynamic

performance.

The lowest typical conversion rate of the AD6642 is 40 MSPS.

At clock rates below 40 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD6642 provides a data clock output (DCO) signal

intended for capturing the data in an external register. The

output data for Channel A is valid on the rising edge of DCO;

the output data for Channel B is valid on the falling edge of

DCO. See Figure 2 for a graphical timing description.

Table 11. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

< −VREF − 0.5 LSB

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= −VREF

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= 0

1000 0000 0000 0000

0000 0000 0000 0000

VIN+ − VIN−

= +VREF − 1.0 LSB

1111 1111 1111 1111

0111 1111 1111 1111

VIN+ − VIN−

> +VREF − 0.5 LSB

1111 1111 1111 1111

0111 1111 1111 1111

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