AD6642BBCZRL datasheet(7/32 Pages) AD

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AD6642

Rev. 0 | Page 7 of 32

Parameter

Temperature

Min

Typ

Max

Unit

Input Resistance

Full

kΩ

Input Capacitance

Full

LOGIC INPUT (PDWN)2

High Level Input Voltage

Full

1.22

2.1

Low Level Input Voltage

Full

0.6

High Level Input Current

Full

−90

−134

μA

Low Level Input Current

Full

−10

+10

μA

Input Resistance

Full

kΩ

Input Capacitance

Full

DIGITAL OUTPUTS (LVDS)

Differential Output Voltage (VOD)

Full

247

454

Output Offset Voltage (VOS)

Full

1.125

1.375

1 Pull up.

2 Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 4.

Parameter

Temperature

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate1

Full

185

200

MSPS

CLK Pulse Width High (tCH)

Full

2.7

Aperture Delay (tA)

Full

1.3

Aperture Uncertainty (Jitter, tJ)

Full

0.13

ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)

Full

3.0

4.35

5.7

DCO Propagation Delay (tDCO)

Full

3.2

4.55

5.9

DCO to Data Skew (tSKEW)

Full

−0.4

−0.2

Pipeline Delay (Latency)

Full

Cycles

With NSR Enabled

Full

Cycles

Wake-Up Time2

Full

1.2

μs

OUT-OF-RANGE RECOVERY TIME

Full

Cycles

1 Conversion rate is the clock rate after the divider.

2 Wake-up time is dependent on the value of the decoupling capacitors.

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