MPC8533ECHXAAJB datasheet(64/116 Pages) FREESCALE

64 / 116 page

MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

•

Single-ended Mode

— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude

(single-ended swing) must be between 400 and 800 mV peak-peak (from Vmin to Vmax) with

SDn_REF_CLK either left unconnected or tied to ground.

—The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 44 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC

or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as

the clock input (SDn_REF_CLK) in use.

Figure 42. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 43. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 44. Single-Ended Reference Clock Input DC Requirements

n_REF_CLK

Vmax < 800 mV

Vmin > 0 V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

n_REF_CLK

Vcm

200 mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm - 400 mV

n_REF_CLK

400 mV < SDn_REF_CLK Input Amplitude < 800 mV

MPC8533ECHXAAJB Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc