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TMS320VC549 Datasheet(PDF) 73 Page - Texas Instruments |
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TMS320VC549 Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 111 page  TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 73 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port read (IOSTRB = 0)†‡ (see Figure 18) PARAMETER ’LC542-40 ’LC543-40 ’C54x-40 ’LC54x-40 ’LC54x-50 ’54x-66 UNIT MIN MAX MIN MAX MIN MAX td(CLKL-A) Delay time, address valid from CLKOUT low 0 5 0 5 0 5 ns td(CLKH-ISTRBL) Delay time, IOSTRB low from CLKOUT high 0 5 0 5 – 2 3 ns td(CLKH-ISTRBH) Delay time, IOSTRB high from CLKOUT high – 2 3 – 2 3 – 2 3 ns th(A)IOR Hold time, address after CLKOUT low 0 5 0 5 0 5 ns † Address and IS timings are included in timings referenced as address. ‡ See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance. |
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