AT52SC1283J datasheet(46/52 Pages) ATMEL

46 / 52 page

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

50. Write Cycle Waveforms

50.1

Write Cycle (1)

(PWE Controlled, ZZ = V

IH)

50.2

Write Cycle (2)

(PCS1 Controlled, ZZ = V

IH)

50.3

Write Cycle (3)

(PUB, PLB Controlled, ZZ = V

IH)

Notes:

1. A write occurs during the overlap (t

WP) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with

asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write

ends at the earliest transition when PCS1 goes high and PWE goes high. The t

WP is measured from the beginning of write to

the end of write.

2. t

CW is measured from the PCS1 going low to end of write.

3. t

AS is measured from the address valid to the beginning of write.

4. t

WR is measured from the end of write to the address change. tWR applied in case a write ends as PCS1 or PWE going high.

5. Do not access device with cycle timing shorter than t

RC (tWC) for continuous periods > 10 µs.

Address

PCS1

PUB, PLB

PWE

Data Out

High-Z

Data Undefined

Data Valid

Data In

(2)

(1)

(4)

Address

PCS1

PUB, PLB

PWE

Data Out

High-Z

Data Valid

Dat a In

(2)

(1)

(4)

Address

PCS1

PUB, PLB

PWE

Data Out

High-Z

Data Valid

Data In

(2)

(1)

(4)

AT52SC1283J Datasheet(PDF) 46 Page - ATMEL Corporation

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