AT52SC1283J datasheet(21/52 Pages) ATMEL

21 / 52 page

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

Notes:

1. Default State

2. Burst configuration setting of B13 - B11 = 010 (clock latency of two), B9 = 1 (hold data for two clock cycles) and B8 = 1

(WAIT asserted one clock cycle before data is valid) is not supported.

3. Data is not ready when WAIT is asserted.

Figure 10-1. Output Configuration

Burst Configuration Register

B15

(1)

Synchronous Burst Reads Enabled

Asynchronous Reads Enabled

B14

(1)

Four-word Page

B13 - B11:

010

(2)

011

100

101

110

(1)

Clock Latency of Two

Clock Latency of Three

Clock Latency of Four

Clock Latency of Five

Clock Latency of Six

B10

(1)(3)

WAIT Signal is Asserted Low

WAIT Signal is Asserted High

(1)

Hold Data for One Clock

Hold Data for Two Clocks

(1)

WAIT Asserted during Clock Cycle in which Data is Valid

WAIT Asserted One Clock Cycle before Data is Valid

(1)

Linear Burst Sequence

(1)

Burst Starts and Data Output on Falling Clock Edge

Burst Starts and Data Output on Rising Clock Edge

B5 - B4

(1)

Reserved for Future Use

(1)

Wrap Burst Within Burst length set by B2 - B0

Don’t Wrap Accesses Within Burst Length set by B2 - B0

B2 - B0

001

010

011

111

(1)

Four-word Burst

Eight-word Burst

Sixteen-word Burst

Continuous Burst

10. Clock Latency versus Input Clock Frequency

Minimum Clock Latency

(Minimum Number of Clocks Following Address Latch)

Input Clock Frequency

5, 6

≤ 66 MHz

≤ 61 MHz

2, 3

≤ 40 MHz

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

CLK

I/00 - I/015

1 CLK

Data Hold

(B9 = 0)

2 CLK

Data Hold

(B9 = 1)

AT52SC1283J Datasheet(PDF) 21 Page - ATMEL Corporation

AT52SC1283J Datasheet(HTML) 21 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Descarga

Enlace URL