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MPC8610EC Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc |
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MPC8610EC Datasheet(HTML) 82 Page - Freescale Semiconductor, Inc |
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82 / 96 page  MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Hardware Design Considerations Freescale Semiconductor 82 Figure 53. JTAG Interface Connection 3.10 Guidelines for High-Speed Interface Termination 3.10.1 SerDes Interface The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:2] and through the DEVDISR register in software. If a SerDes port is disabled through the POR input the user can not enable it through the DEVDISR register in HRESET HRESET From Target Board Sources HRESET 13 SRESET SRESET SRESET NC NC 11 VDD_SENSE 6 5 1 15 2 k Ω 10 k Ω 10 k Ω 10 k Ω OVDD OVDD OVDD OVDD CKSTP_IN CKSTP_IN 8 TMS TDO TDI TCK TMS TDO TDI TCK 9 1 3 4 TRST 7 16 2 10 12 (if any) 14 2 Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented. Connect pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor. 2. Key location; pin 14 is not physically present on the COP header. OVDD OVDD 10 k Ω OVDD TRST 10 k Ω OVDD 10 k Ω 10 k Ω CKSTP_OUT CKSTP_OUT 3 13 9 5 1 6 10 15 11 7 16 12 8 4 KEY No pin COP Connector Physical Pin Out 1 2 NC |
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