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M38040F2HKP Datasheet(PDF) 214 Page - Renesas Technology Corp |
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M38040F2HKP Datasheet(HTML) 214 Page - Renesas Technology Corp |
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214 / 387 page ![]() 2-90 APPLICATION 2.5 Multi-master I2C-BUS interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.5.8 Structure of I2C START/STOP condition control register I2C special mode control register b7 b6 b5 b4 b3 b2 b1 b0 I2C special mode control register (S3D: address 001716) b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 0 0 0 0 0 0 0: At communication completion 1: At falling of ACK clock and communication completion ACK interrupt control bit (ACKICON) 0: One-byte slave address compare mode 1: Three-byte slave address compare mode Slave address control bit (MSLAD) Writing 1 to this bit initializes the SCL pin low hold 2 flag to 1 . (Notes 1, 2) SCL pin low hold 2 flag set bit (PIN2IN) Writing 1 to this bit clears the SCL pin low hold 2 flag to 0 and holds the SCL pin low. (Notes 1, 2) SCL pin low hold set bit (PIN2HD) STOP condition flag clear bit (SPFCL) Writing 1 to this bit initializes the STOP condition flag to 0. (Note 1) Notes 1: When 0 is written to these bits, nothing is happened. 2: Do not write 1 to these bits at the same time. ✕ Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . Fix this bit to 0 . 0 0 Fix this bit to 0 . Fig. 2.5.9 Structure of I2C special mode control register I2C START/STOP condition control register b7 b6 b5 b4 b3 b2 b1 b0 I2C START/STOP condition control register (S2D: address 001616) b 0 Name 0 Functions At reset R W 1 0 1 1 1 2 3 4 0 0: Falling edge active 1: Rising edge active SCL release time = φ (µs) ✕ (SSC+1) Setup time = φ (µs) ✕ (SSC+1)/2 Hold time = φ (µs) ✕ (SSC+1)/2 0: SDA valid 1: SCL valid 5 0 SCL/SDA interrupt pin polarity selection bit (SIP) 7 6 0 Fix this bit to 0 . START/STOP condition set bits (SSC0, SSC1, SSC2, SSC3, SSC4) SCL/SDA interrupt pin selection bit (SIS) Note: Fix SSC0 to 0 . Also, do not set SSC4 to SSC0 to odd values or 000002 . 0 |
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