M38040F2HKP datasheet(213/387 Pages) RENESAS

213 / 387 page

2-89

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

I2C clock control register

b7 b6 b5 b4 b3 b2 b1 b0

I2C clock control register

(S2: address 001516)

Name

Functions

At reset R W

0: Standard clock mode

1: High-speed clock mode

0: ACK is returned.

1: ACK is not returned.

SCL mode

specification bit

(FAST MODE)

ACK clock bit

(ACK)

00 to 02

Disabled

333

(Note 2)

250

100

400 (Note 3)

83.3

166

500/CCR value 1000/CCR value

(Note 3)(Note 3)

17.2

34.5

16.6

33.3

16.1

32.3

(

φ = 4 MHz, Unit: kHz) (Note 1)

0: No ACK clock

1: ACK clock

Setting value

b4b3b2b1b0

Standard

clock mode

High-speed

clock mode

SCL frequency

control bits

(CCR0, CCR1,

CCR2, CCR3,

CCR4)

ACK bit

(ACK BIT)

Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-

speed clock mode is selected and CCR value = 5 (400 kHz, at

φ = 4 MHz). H

duration of the clock fluctuates from —4 to +2 machine cycles in the standard clock

mode, and fluctuates from —2 to +2 machine cycles in the high-speed clock mode. In

the case of negative fluctuation, the frequency does not increase because L

duration is extended instead of H duration reduction.

These are values when SCL clock synchronization by the synchronous function is not

performed. CCR value is the decimal notation value of the SCL frequency control bits

CCR4 to CCR0.

2: Each value of SCL frequency exceeds the limit at

φ = 4 MHz or more. When using

these setting value, use

φ of 4 MHz or less.

3: The data formula of SCL frequency is described below:

φ/(8 ✕ CCR value) Standard clock mode

φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)

φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)

Do not set 0 to 2 as CCR value regardless of

φ frequency.

Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed

clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to

CCR0.

Fig. 2.5.7 Structure of I2C clock control register

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