HD64F2149YV datasheet(198/1075 Pages) RENESAS

No. de pieza	HD64F2149YV

Descripción Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 170 of 1044

REJ09B0280-0300

7.2

7.2.1

DTC Mode Register A (MRA)

SM1

SM0

DM1

DM0

MD1

MD0

DTS

Bit

Initial value

Read/Write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

MRA is an 8-bit register that controls the DTC operating mode.

Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is

to be incremented, decremented, or left fixed after a data transfer.

Bit 7

Bit 6

SM1

SM0

Description

—

SAR is fixed

SAR is incremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

SAR is decremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether

DAR is to be incremented, decremented, or left fixed after a data transfer.

Bit 5

Bit 4

DM1

DM0

Description

—

DAR is fixed

DAR is incremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

DAR is decremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

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