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HD64F2149YV Datasheet(PDF) 93 Page - Renesas Technology Corp

No. de pieza HD64F2149YV
Descripción Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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HD64F2149YV Datasheet(HTML) 93 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 3.00 Jan 18, 2006 page 65 of 1044
REJ09B0280-0300
Table 2.6
Effective Address Calculation
No.
Addressing Mode and
Instruction Format
Effective Address
Calculation
Effective Address (EA)
1
Register direct (Rn)
op
rm rn
Operand is general register
contents.
2
Register indirect (@ERn)
General register contents
31
0
31
0
r
op
24 23
Don’t
care
3
Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
General register contents
Sign extension
disp
31
0
31
0
31
0
op
r
disp
Don’t
care
24 23
4
Register indirect with post-increment or pre-decrement
• Register indirect with post-increment @ERn+
General register contents
1, 2, or
4
31
0
31
0
r
op
Don’t
care
24 23
• Register indirect with pre-decrement @–ERn
General register contents
1, 2, or
4
Byte
Word
Longword
1
2
4
Operand
Size
Value
Added
31
0
31
0
op
r
Don’t
care
24 23



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