HD64F2149YV datasheet(175/1075 Pages) RENESAS

No. de pieza	HD64F2149YV

Descripción Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Section 6 Bus Controller

Rev. 3.00 Jan 18, 2006 page 147 of 1044

REJ09B0280-0300

6.3.4

I/O Select Signal

In the H8S/2169 or H8S/2149, an I/O select signal (

IOS) can be output, with the signal output

going low when the designated external space is accessed.

Figure 6.2 shows an example of

IOS signal output timing.

Address bus

IOS

Bus cycle

External address in IOS set range

Figure 6.2

IOS

IOS Signal Output Timing

Enabling or disabling of

IOS signal output is controlled by the setting of the IOSE bit in SYSCR.

In expanded mode, this pin operates as the

AS output pin after a reset, and therefore the IOSE bit

in SYSCR must be set to 1 in order to use this pin as the

IOS signal output. See section 8, I/O

Ports, for details.

The range of addresses for which the

IOS signal is output can be set with bits IOS1 and IOS0 in

BCR. The

IOS signal address ranges are shown in table 6.4.

Table 6.4

IOS

IOS Signal Output Range Settings

IOS1

IOS0

IOS

IOS Signal Output Range

H'(FF)F000 to H'(FF)F03F

H'(FF)F000 to H'(FF)F0FF

H'(FF)F000 to H'(FF)F3FF

H'(FF)F000 to H'(FF)F7FF

(Initial value)

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