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HD64F2149YV Datasheet(PDF) 363 Page - Renesas Technology Corp

No. de pieza HD64F2149YV
Descripción Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
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HD64F2149YV Datasheet(HTML) 363 Page - Renesas Technology Corp

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Section 11 16-Bit Free-Running Timer
Rev. 3.00 Jan 18, 2006 page 335 of 1044
REJ09B0280-0300
11.3.7
Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 11.13 shows the timing of this operation.
H'FFFF
H'0000
Overflow signal
φ
FRC
OVF
Figure 11.13 Setting of Overflow Flag (OVF)
11.3.8
Automatic Addition of OCRA and OCRAR/OCRAF
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. The OCRA write timing is shown in figure 11.14.
OCRAR,
OCRAF
OCRA
FRC
φ
A
N
N+A
Compare-match
signal
N
N+1
Figure 11.14 OCRA Automatic Addition Timing



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